Stacked die for 3-dimensional integration (3-DI) are rapidly becoming a reality for commercial applications, including field-programmable gate arrays (FPGAs) and memory devices. Generally, 3-DI employs through silicon vias (TSVs) filled with a conductive material (e.g., Cu or W) to provide vertical electrical connections to a die. Further electrical pathways can be facilitated by using conductive solder bumps between a die and another component (e.g., another die, a circuit board, an interposer, etc.), in which such bumps are generally surrounded by a polymer underfill.
From a failure analysis perspective, 3-DI presents many challenges in order to access such electrical components, such as TSVs and solder bumps. For instance, the die of interest can be obstructed by other stacked die. Alternatively, the die of interest can be extremely thin and fragile, which can be difficult to handle. Many techniques involved with the preparation of 3-DI for failure analysis are destructive, in which a die has to be separated to access internal components, thereby resulting in loss of device functionality. Accordingly, there is an emerging need for semi-destructive processes to access and to connect targeted TSVs and/or solder bumps on 3-DI components, such as those that are sandwiched between the stacked die and/or are not accessible from the large faces of the die stack.